In reply to chr_sue:
Hi Chr_sue,
Now same scenario Registers WR/RD i am doing through RAL model. Write Transaction is going well but I am not seeing the read transaction at Interface.
Sequence Code :-
task body;
uvm_status_e status;
uvm_reg_data_t incoming;
bit [31:0] rdata;
if (starting_phase != null)
starting_phase.raise_objection(this);
//Write to the Registers
m_sfr_aon_reg_model.FW_SPARE0.write(status,32'haaaa_5555);
//Read from the registers
m_sfr_aon_reg_model.FW_SPARE0.read(status, rdata);
if (starting_phase != null)
starting_phase.drop_objection(this);
endtask
Adapter Code :
virtual function uvm_sequence_item reg2bus( const ref uvm_reg_bus_op rw );
svci_cmd_trans_pkt cmd_tx = svci_cmd_trans_pkt::type_id::create("cmd_tx");
`uvm_info("REG2BUS",$sformatf("Entered reg2bus at time = %0t",$time),UVM_LOW)
cmd_tx.cmd_addr = rw.addr;
if ( rw.kind == UVM_READ ) begin
$display ("adapter read");
cmd_tx.cmd_opc = 'h0;
//cmd_tx.cmd_len = rd_cmd_len;
cmd_tx.cmd_len = 'h2;
`uvm_info("REG2BUS", $sformatf(" read access = %s", cmd_tx.cmd_opc.name), UVM_LOW)
end
else if ( rw.kind == UVM_WRITE ) begin
$display ("adapter write");
//cmd_tx.cmd_opc = wr_type ? NON_POSTED_WRITE : POSTED_WRITE ;
cmd_tx.cmd_opc = NON_POSTED_WRITE ;
//cmd_tx.cmd_len = wr_cmd_len;
cmd_tx.cmd_len = 'h2;
cmd_tx.cmd_mid = 'h0;
//cmd_tx.cmd_tag = rand_val_tag;
cmd_tx.cmd_tag = 'h0;
cmd_tx.cmd_wdata = rw.addr[2]? {rw.data[31:0],32'h0} : {32'h0,rw.data[31:0]};
//`uvm_info("REG2BUS", $sformatf(" Address = %h, Data = %h, access = %s", cmd_tx.cmd_addr, cmd_tx.cmd_wdata, cmd_tx.cmd_opc.name), UVM_MEDIUM)
`uvm_info("REG2BUS", $sformatf(" Address = %h, Data = %h, access = %s", cmd_tx.cmd_addr, cmd_tx.cmd_wdata, cmd_tx.cmd_opc.name), UVM_LOW)
end
return cmd_tx;
endfunction: reg2bus
virtual function void bus2reg( uvm_sequence_item bus_item, ref uvm_reg_bus_op rw );
svci_cmd_trans_pkt cmd_tx = svci_cmd_trans_pkt::type_id::create("cmd_tx");
svci_rsp_reg_pkt rsp_tx = svci_rsp_reg_pkt ::type_id::create("rsp_tx");
if($cast( rsp_tx, bus_item))begin
rw.kind = ( rsp_tx.rsp_type ==READ ) ? UVM_READ : UVM_WRITE;
rw.addr = rsp_tx.rsp_addr;
rw.data = rsp_tx.rsp_rdata;
rw.status = UVM_IS_OK;
`uvm_info("BUS2REG", $sformatf(" :: 2 :: Address = %h, Data = %h, access = %s", rsp_tx.rsp_addr,rsp_tx.rsp_rdata, rsp_tx.rsp_opc.name), UVM_LOW)
end
endfunction: bus2reg
Could you give me any hint how to debug this scenario ?
when i do not use RAL model it work very well (which has been explained in earlier post).