How to create an iterative pattern in a long vector bit

SystemVerilog
1

Hey VA,

Need to populate memory array, each line is of width 128bits.
Looking for a beautiful way to create data patterns inside the each line.

Examples:
0x0000_0777_0000_0777_0000_0777_0000_0777 (used next code for this: cache_mem[i] = {4{i}};)
0x059a_059a_059a_059a_059a_059a_059a_059a

looking to understand how to do it and understand the replication operator more thoroughly.

Thanks,
Michael

2

In reply to Michael54:

Use “+:”.


reg [127:0] tmp;

for(int i=0; i<128; i=i+16)
  tmp[i +: 16] = 16'h059a;

In detail, look at § 11.5.1 “Vector bit-select and part-select addressing” in IEEE1800-2017.

3

In reply to Michael54:

do you want random data to be populated using replication operator?

To understand replication operator, refer IEEE Std 1800-2017
5.10 Structure literals
5.11 Array literals
11.4.12.1 Replication operator

'{2 {y}} ; // same as ‘{y, y}
‘{2{’{3{y}}}}; // same as ‘{’{y,y,y},’{y,y,y}}

If you want random repeated data then try something like this


module test;

  bit [15:0] d1, d2;
  bit [7:0][15:0] mem;
    
  initial begin
    repeat(50) begin
      std::randomize(d1,d2) with { {d1,d2} inside {[0:'hffff]} dist {1:=50, 0:=50};};
      mem = '{4{d1,d2}};
      $display("mem=0x%x", mem);
    end
  end

endmodule

/*
Sim result:
mem=0x00001d6700001d6700001d6700001d67
mem=0xe5d57e65e5d57e65e5d57e65e5d57e65
mem=0x0000fcbf0000fcbf0000fcbf0000fcbf
mem=0x3b1411903b1411903b1411903b141190
mem=0x00001a8e00001a8e00001a8e00001a8e
mem=0x53125763531257635312576353125763
mem=0xd65114a0d65114a0d65114a0d65114a0
mem=0x000098c2000098c2000098c2000098c2
mem=0xd5eb919fd5eb919fd5eb919fd5eb919f
mem=0x000083ba000083ba000083ba000083ba
mem=0x0000a37a0000a37a0000a37a0000a37a
mem=0xb844fc3fb844fc3fb844fc3fb844fc3f
mem=0x000007ca000007ca000007ca000007ca
/*