How to create an iterative pattern in a long vector bit

SystemVerilog
2

In reply to Michael54:

Use “+:”.


reg [127:0] tmp;

for(int i=0; i<128; i=i+16)
  tmp[i +: 16] = 16'h059a;

In detail, look at § 11.5.1 “Vector bit-select and part-select addressing” in IEEE1800-2017.