I made an alu.sv module (with simple SystemVerilog code blocks like 5'b00000: alu_out = a + b; // ADD) that is thoroughly tested with its own testbench that I already created. In total, the ALU has thirteen different functions (ADD, SUB, MUL, etc.).
I followed this video to make my ALU’s testbench (with an external file): https://youtu.be/Hu9V0_ffp30?si=hJz5uN5JNv9nHdnR
I also built a main.sv file to wrap the ALU module inside it with: one clock (all components on posedge), one program counter (range from 0 to 7), one 16-bit wide RAM (to store two 8-bit wide operands a and b that will go INTO the ALU) with 256 unique locations (range from 0 to 255), the ALU module (from alu.sv == accepts two 8-bit operands, performs one function according to a 5-bit opcode passed (here, a 5-bit opcode corresponds to a specific function (like 00000 == ADD)), gives an 8-bit output stored in alu_out), and one register that stores an 8-bit number on posedge. This completes the introduction.
What I actually need is a testbench that can test my main.sv thoroughly (challenging my circuit to find holes).
I am new to testbench creation and its related concepts. One thing I saw a while ago is the Universal Verification Methodology (UVM) to create testbenches according to the universal standard. Is there any use of the methodology in my circuit or my circuit is too simple to include that?
