How to create a define for an SystemVerilog escaped name in a command line call

SystemVerilog
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1

I would like to create a define called MOD_PATH to an instance of module that contains parameters. So, instance name is created as an escaped name.
So I trying to pass it by command line as

"–define MOD_PATH=\\top.module(DATA_WITDH=8,MODEL="TYPE_A")\ "

and trying to use as (in SV testcase)

`MOD_PATH.task_a();

However, it expanded for “\top.module(DATA=8,MODEL=“TYPE_A”)” and last space seems not appears.
So module is not found. Hardcode it is working.

Any suggestions?

2

In reply to joao.fragoso:

This might be a tool or shell specific issue. But I think the best option would be to put a period(.) in the macro after the space.

"--define MOD_PATH=\\\\top.module(DATA_WITDH=8,MODEL=\"TYPE_A\") ."

`MOD_PATH task_a();
3

In reply to dave_59:

Sorry for my late reply, but it did not work, since it get expanded with a space after the dot:
\top.module(DATA=8,MODEL=“TYPE_A”) . task_a();

and the path is not recognized.