How to create a define for an SystemVerilog escaped name in a command line call

SystemVerilog
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2

In reply to joao.fragoso:

This might be a tool or shell specific issue. But I think the best option would be to put a period(.) in the macro after the space.

"--define MOD_PATH=\\\\top.module(DATA_WITDH=8,MODEL=\"TYPE_A\") ."

`MOD_PATH task_a();