How to constrain the 2nd dimension of a 2D array in systemverilog

In reply to nikhilac@nvidia.com:
Please use code tags making your code easier to read. I have added them for you.

class A ;
  rand bit[1:0] mem[2][16];
  constraint C1{foreach(mem[i,j]) mem[i][j] inside {0,1};}
  constraint C2{foreach(mem[i]) mem[i].sum() with (int'(item)) <= 2 ;} // you said "no more than 2"
  constraint C3{foreach(mem[,j]) mem.sum() with (int'(mem[item.index][j])) != 2 ;}
endclass

module t();
  A a_h = new();
  initial repeat(5) begin
      a_h.randomize();
      $display("value is %p", a_h.mem); 
   end 
endmodule

Notice the different foreach iterators