How to constrain the 2nd dimension of a 2D array in systemverilog

SystemVerilog
2

In reply to nikhilac@nvidia.com:


class A ;

  rand bit[1:0] mem[2][4];
  rand bit[1:0] mem_hlpr[4][2];

  constraint C1 {foreach(mem[i,j]) mem[i][j] inside {0,1};}
  constraint C1_1 {foreach(mem_hlpr[i,j]) mem_hlpr[i][j] inside {0,1};}
  constraint C2{foreach(mem[i,j]) mem[i].sum() with (int'(item)) == 2 ;}
  constraint C3{foreach(mem_hlpr[i,j]) mem_hlpr[i].sum() with (int'(item)) != 2 ;}
  constraint C4{foreach(mem[i,j]) mem[i][j] == mem_hlpr[j][i];}

endclass