How to compile UVM-1.2_RC1?

UVM
1

I tried to run UVM 1.2 RC1 with Questa, but it seems to be broken. The main issues are below. How can I work around these issues?

**# ** Error: (vsim-3978) /proj/uvm-1.2/src/base/uvm_transaction.svh(487): Illegal assignment to class work.uvm_pkg::uvm_event #(class work.uvm_pkg::uvm_object) from unknown class type

Time: 0 ns Iteration: 0 Region: /uvm_pkg File: /proj/uvm-1.2/src/uvm_pkg.sv

** Error: (vsim-3978) /proj/uvm-1.2/src/base/uvm_transaction.svh(676): Illegal assignment to class work.uvm_pkg::uvm_event #(class work.uvm_pkg::uvm_object) from unknown class type

Time: 0 ns Iteration: 0 Region: /uvm_pkg File: /proj/uvm-1.2/src/uvm_pkg.sv

** Error: (vsim-3978) /proj/uvm-1.2/src/base/uvm_component.svh(2597): Illegal assignment to class work.uvm_pkg::uvm_event #(class work.uvm_pkg::uvm_object) from unknown class type

Time: 0 ns Iteration: 0 Region: /uvm_pkg File: /proj/uvm-1.2/src/uvm_pkg.sv

** Error: (vsim-3978) /proj/uvm-1.2/src/base/uvm_component.svh(2810): Illegal assignment to class work.uvm_pkg::uvm_event #(class work.uvm_pkg::uvm_object) from unknown class type

Time: 0 ns Iteration: 0 Region: /uvm_pkg File: /proj/uvm-1.2/src/uvm_pkg.sv

** Error: (vsim-3978) /proj/uvm-1.2/src/base/uvm_component.svh(2762): Illegal assignment to class work.uvm_pkg::uvm_event #(class work.uvm_pkg::uvm_object) from unknown class type

Time: 0 ns Iteration: 0 Region: /uvm_pkg File: /proj/uvm-1.2/src/uvm_pkg.sv

Error loading design**

I tried with Questa 10.1d and 10.2c.

2

UVM 1.2RC1 was just released yesterday and vendors are just now analyzing the package. Trying to fix these yourself would be a duplication of effort. You could try Questa 10.3; I doubt any earlier versions of Questa will be supported.

3

The issue is with forward declaration of parametrized classes. I was able to reproduce it with this simple SystemVerilog example:

typedef class my_object;
typedef class my_object_pool;

class my_transaction;

  const my_object_pool#(my_object) pool = new;
  
  function new();
    my_object#() a = pool.get();
  endfunction

endclass

module test;

  initial begin
    automatic my_transaction tr = new;
  end

endmodule

class my_object#(type T=int);
endclass

class my_object_pool#(type T=my_object);

  const T item = new;

  virtual function T get();
    $display("getting item from pool");
    return item;
  endfunction

endclass

**# ** Error: (vsim-3978) testbench.sv(9): Illegal assignment to class work.design_sv_unit::my_object #(int) from unknown class type
**

Any way to fix it besides re-ordering the compile order?

4

In reply to dave_59:

Got it working with this small change at the bottom of uvm_pool.svh:

class uvm_event_wrapper extends uvm_event#();
  function new (string name="");
    super.new(name);
  endfunction
endclass
typedef uvm_object_string_pool #(uvm_event_wrapper) uvm_event_pool;