How to compile UVM-1.2_RC1?

UVM
3

The issue is with forward declaration of parametrized classes. I was able to reproduce it with this simple SystemVerilog example:

typedef class my_object;
typedef class my_object_pool;

class my_transaction;

  const my_object_pool#(my_object) pool = new;
  
  function new();
    my_object#() a = pool.get();
  endfunction

endclass

module test;

  initial begin
    automatic my_transaction tr = new;
  end

endmodule

class my_object#(type T=int);
endclass

class my_object_pool#(type T=my_object);

  const T item = new;

  virtual function T get();
    $display("getting item from pool");
    return item;
  endfunction

endclass

**# ** Error: (vsim-3978) testbench.sv(9): Illegal assignment to class work.design_sv_unit::my_object #(int) from unknown class type
**

Any way to fix it besides re-ordering the compile order?