How to check clock frequency through asserions

UVM
1

Hi,
I have a clk frequency randomized between 10Mhz -100Mhz and want to check the frequency through assertions … whether frequency is correct or not ,Can any one help me , how to resolve below error…and I am using cadence ncsim…

//Checking clock period range
assert property (period_chk)
else
$error(0,“Wrong clock frequency”,$time);

property period_chk;
time current_time;
$rose(smb_clk) ('1,current_time = $time/1000000) |-> $rose(smb_clk) (($time/1000000)-current_time <= 100) && ($time/1000000)-current_time >= 10));
endproperty

Error :
$rose(smb_clk) ('1,current_time = $time/1000000) |-> $rose(smb_clk) (($time/1000000)-current_time <= 100) && ($time/1000000)-current_time >= 10));
|
ncvlog: *E,ALXSCN (/iel-storage1/home/sdasari/SMBUS_VIP/verif/tb/smbus_assertions.sv,48|19): Expected specification terminator “;”.

2

I understand that you want to trigger the time sampling at one posedge of smb_clk and check if the time difference is within the desired range at the following posedge.

For this, you should change $rose with @(posedge smb_clk) (to trigger the sampling), and use the non-overlapping implication operator |=> instead of |-> so that the next posedge does not overlap with the current one, like this :

property period_chk;
    time current_time;
    @(posedge smb_clk) (1, current_time = $time/1000000) |=> @(posedge smb_clk)      (($time/1000000-current_time <= 100) && ($time/1000000-current_time >= 10));
endproperty
3

The following would be easier. Add the timeunit, timeprecision.


module timem;
   timeunit 1ns; timeprecision 100ps;
   bit clk, a, b; 
   initial forever #5 clk=!clk; 
	
   property period_chk;
      time current_time;
       ('1,current_time = $time ) ##1 
       	  ($time -current_time == 10ns);  
   endproperty
   ap_time: assert property(@(posedge clk) period_chk); 
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
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