Can anyone help to write assertion for 200MHz clk check?

[dave_59]

How to check clock frequency through asserions

The following would be easier. Add the timeunit, timeprecision. module timem; timeunit 1ns; timeprecision 100ps; bit clk, a, b; initial forever #5 clk=!clk; property period_chk; time current_time; ('1,current_time = $time ) ##1 ($time -current_time == 10ns); endproperty ap_time: assert property(@(posedge clk) period_chk); endmodule Ben Cohen http://www.systemverilog.us/ ben@systemverilog.us SystemVerilog Assertions Handbook 3rd Edition, 2…