How to check a signal to be one for 'n' clocks in SVA

SystemVerilog
, ,
3

In reply to ben@SystemVerilog.us:

Hi Ben,

I think above property does not check whether Signal a reamins high for all 5 clocks so can we write this as

(rose(a), v=g) |-> (a==1'b1, v=v-1'b1)[*1:] ##0 v==1’b0 ##0 a==1’b1;

Thanks & Regards
Raku