How to check a signal to be one for 'n' clocks in SVA

SystemVerilog
, ,
2

I want to check a signal to be high for n clocks where n can be configurable local variable


module m; 
  bit clk, a, b; 
  int g=5; 
  property p_g; 
   int v; 
   ($rose(a), v=g) |-> (1'b1, v=v-1'b1)[*1:$] ##0 v==1'b0;
  endproperty
  ap_g: assert property(@ (posedge clk) p_g);

Ben Cohen http://www.systemverilog.us/

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