How to check a signal for 20 clock cycle within a sequence

UVM
,
1

How to check that a signal if occur will last for 20 cycles within a sequence?
i.e @(posedge vif.clk) if(vif.a==1’b1) then vif.b should be 1’b0 for 20 cycles.
Thanks

2

In reply to suvendra kumar sahoo:

This is better written as a simple assertion inside your interface

assert property (( @posedge clk) a |-> !b[*20]);
3

In reply to dave_59:

You need a $rose(a) if “a” is not a single pulse.
Ben Systemverilog.Us