How to catch this bug

SystemVerilog
,
1

Hi,

I have a RAM of 1KB memory.
When I do a write to memory location A, The write is happening to memory location B.
When I do a read from memory location A, The read is happening from memory location B.
When I do a write to memory location B, The write is happening to memory location A.
When I do a read from memory location B, The read is happening from memory location A.
But doing read and write with random data I will not be able to catch this bug. Can anyone suggest me how to catch this bug.

2

In reply to Ravi007:

You are trying to confirm that the correct memory bit word line is triggered. If you issued a write or read and if the word line is triggered after 3 cycles or N cycles dep on the design pipeline. you can check that whenever the wordline is generated you go back in time to find the address corresponding to the write/read which triggers the word line later after a few cycles and match it against this address.

property p_Addr_WL_Bits_Match(wl);
@(posedge clock)
if(|wl)
wl == ( 512’b1<<($past(addr[8:0],3)) );
endproperty: p_Addr_WL_Bits_Match
ap_Memory_Addr_WL_Bit_Match: assert property (p_Addr_WL_Bits_Match(wordline)) else
//throw in a useful error condition

There is another way to do it, you can store the address in the cycle you are issuing a write or read and then use it later in time to check the word line against this stored value. Refer to the interleaving request assertion example under courses-> Assertion based verification (session6 talks about this using an arbiter example)

3

In reply to Ravi007:

If you have a single read/write port in your memory, you won’t be able to detect this bug using simple reads and writes. Also, this bug isn’t really a bug as the functionality is correct in that the data written to an address and read from an address is the same. The only time there would be an error is if you have write collisions.

If you have multiple read/write ports, then you may see this as a bug. To test, you would need to write every location via one port, and read every location from the other port, and vice versa. You could then detect any data mismatches.