In reply to Ravi007:
You are trying to confirm that the correct memory bit word line is triggered. If you issued a write or read and if the word line is triggered after 3 cycles or N cycles dep on the design pipeline. you can check that whenever the wordline is generated you go back in time to find the address corresponding to the write/read which triggers the word line later after a few cycles and match it against this address.
property p_Addr_WL_Bits_Match(wl);
@(posedge clock)
if(|wl)
wl == ( 512’b1<<($past(addr[8:0],3)) );
endproperty: p_Addr_WL_Bits_Match
ap_Memory_Addr_WL_Bit_Match: assert property (p_Addr_WL_Bits_Match(wordline)) else
//throw in a useful error condition
There is another way to do it, you can store the address in the cycle you are issuing a write or read and then use it later in time to check the word line against this stored value. Refer to the interleaving request assertion example under courses-> Assertion based verification (session6 talks about this using an arbiter example)