In reply to ben@SystemVerilog.us:
In reply to Yehu:
Why do you say In this case I will get an error message at time that the ‘valid’ is 0.?
The disable iff is asynchronous.
1800’16.12 Declaring properties
The expression of the disable iff is called the disable condition. The disable iff clause allows preemptive resets to be specified. For an evaluation of the property_spec, there is an evaluation of the underlying property_expr. If the disable condition is true at anytime between the start of the attempt in the Observed region, inclusive, and the end of the evaluation attempt, inclusive, then the overall evaluation of the property results in disabled. A property has disabled evaluation if it was preempted due to a disable iff condition. A disabled evaluation of a property does not result in success or failure.
Otherwise, the evaluation of the property_spec is the same as that of the property_expr. The disable condition is tested independently for different evaluation attempts of the property_spec. The values of variables used in the disable condition are those in the current simulation cycle, i.e., not sampled. The expression may contain a reference to an end point of a sequence by using the method triggered of that sequence. The disable conditions shall not contain any reference to local variables or the sequence method matched. If a sampled value function other than $sampled is used in the disable condition, the sampling
clock shall be explicitly specified in its actual argument list as described in 16.9.3. Nesting of disable iff clauses, explicitly or through property instantiations, is not allowed
Another option is explained in 1800’2017 16.12.14 Abort properties
A property is an abort if it has one of the following forms:
accept_on ( expression_or_dist ) property_expr
reject_on ( expression_or_dist ) property_expr
sync_accept_on ( expression_or_dist ) property_expr
sync_reject_on ( expression_or_dist ) property_expr
For an evaluation of accept_on (expression_or_dist) property_expr and of
sync_accept_on (expression_or_dist) property_expr, there is an evaluation of the underlying
property_expr. If during the evaluation, the abort condition becomes true, then the overall evaluation of the property results in true. Otherwise, the overall evaluation of the property is equal to the evaluation of the property_expr.
//Desired code:
property p_clk_freq2;
realtime rising_time;
@(posedge clk) disable iff (!freq_valid)
(1, rising_time=$realtime) |=> accept_on (!freq_valid) @(posedge clk)
($abs(int'(($realtime-rising_time))-int'((period*1.0ps)))<= TOLERANCE);
endproperty
Ben Cohen
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Hi Ben,
is that extra @(posedge clk) needed on the RHS of non overlapping implication operator? I believe it adds one more clock cycle to the calculation.