In reply to ben@SystemVerilog.us:
One more note on making the disable iffsynchronous:
From my SVA book:
Sampled value Function: If a sampled value function other than $sampled is used in the disable condition, the sampling clock must be explicitly specified in its actual argument list. Thus, the following is legal:
apP1: assert property ( // /ch3/3.8/reset2.sv
disable iff ($rose(reset, @(posedge clk)))
• @ (posedge clk) req |=> ack); // disable sampled at @ (posedge clk1)
apP2: assert property (
disable iff ( $sampled(reset))
• @ (posedge clk) req |=> ack);
property pXY(x,y, reset); // active hi reset
int v;
disable iff (reset)
(x, v=0) |=> y && v==data;
endproperty : pXY
apXY_sampled: assert property (@(posedge clk)
pXY(req, ack, $sampled(reset)));
// disable sampled at @ (posedge clk)
**Nesting:**Nesting of disable iff clauses, explicitly or through property instantiations, is not allowed. The disabling condition must only appear at the top level of an assertion. It cannot be nested; this is unlike the accept_on, reject_on, sync_accept_on, sync_reject_on operators that allow nesting (see 3.9.2.14). The following nesting of disable iff example is illegal:
assert property ( @ (posedge clk) disable iff (cancel)
pXY(req, ack, reset)); // pXY has a disable iff
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- SVA Alternative for Complex Assertions
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