Your bind is correct, but the way you are calling set_inner is not correct here. Binding is like secretly instantiating a module/interface within another RTL file without disturbing the existing code. The binded module/interface is instantiated directly into the target module.
Referring to IEEE 1800-2012 example, the cpu is module name, cpu1 is the instance name to which you want to bind the module fpu_props, The instance name of fpu_props is fpu_rules_1.
bind cpu: cpu1, cpu2, cpu3 fpu_props fpu_rules_1(a, b, c);
So, the heirarchy goes like this:
cpu1.fpu_rules_1.<some_signal_in_fpu_props>
cpu2.fpu_rules_1.<some_signal_in_fpu_props>
//... and so on ...
//... in your case, the heirarchy goes as follows:
dutI.A0.m0.set_inner('0);
dutI.A1.m1.set_inner('1);
When you bind to multiple instances, the full hierarchical path changes. As a result, you need to have dutI.A0.m0 and dutI.A1.m1 as calling path.
I have modified your code as below. It runs fine on EDAPlayground with VCS, while Riviera seems to have some simulator specific issues (discussed here and here).
module A(input logic in);
wire inner = in;
always@* $display($time,, "%m: %0b", inner);
endmodule
module dut(input logic in);
A A0(in);
A A1(~in);
endmodule
//using task in interface to manipulate signals
interface bus (output wire inner);
logic in1 = 'z;
assign inner = in1;
task set_inner(input logic value);
in1 = value;
$display("in1 for %m is %0p",in1); // Debug: Full path display
endtask
endinterface
module tb;
logic in;
dut dutI(in);
bind dutI.A0 bus m0(inner); // Binded instance name is m0 for type bus
bind dutI.A1 bus m1(inner); // Binded instance name is m1 for type bus
initial begin
in = 1;
#1 dutI.A0.m0.set_inner('0); // use hierarchy as m0 is binded. Instantiated within A0
#1 dutI.A1.m1.set_inner('1); // use hierarchy as m1 is binded. Instantiated within A1
#1 $finish;
end
endmodule
The CummingsSNUG2009SJ_SVA_Bind Paper is a good source of information for understanding about bind in SystemVerilog.