How to bind inner signals from DUT?

SystemVerilog
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4

In reply to mlsxdx:

This is the result after changing the binding.
0 tb.dutI.A0: x
0 tb.dutI.A1: x
0 tb.dutI.A0: z
1 in1 for tb.dutI.A0.m0.set_inner is 0
1 tb.dutI.A0: 0
2 in1 for tb.dutI.A1.m1.set_inner is 1

@1, tb.dutI.A0: 0 //works as expected
@2, tb.dutI.A1.m1.set_inner //works as expected, the set_inner task get called

Why the always $display not executed?
always@* $display($time, “%m: %0b”, inner);