How to assign uvm testbench varible to VHDL DUT's lower variable

UVM
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1

Hi,

My TB is UVM based and DUT is VHDL based. For that I am written system verilog wrapper file which contain VHDL DUT top instance. Now I have to assign interface signal or any signal from system verilog wrapper file to VHDL DUT’s lower path signal, How to do this?
eg. assign dut_wrapper.dut_top.inst0.tx_data_1 = tx_data;
for this simulation shows fatal error:- Invalid hierarchical access from Verilog instance “/top/dut_wrapper” to non-Verilog object “/top/dut_wrapper/dut_top/inst0/tx_data_1”.

Please help me to solve this issue.

Thanks.

2

In reply to yogeshraut712:

How you accomplish this will be tool dependent. You should read your simulator user manual and contact your vendor with further questions.

3

In reply to yogeshraut712:

There are 2 ways.
(1) The SystemVerilog bind construct allows you to access internal signals in a VHDL design.
(2) If you are using VHDL 2008 you can use the hierarchcal path.

Both options allow only to observe VHDL signals.
If you have a SystemVerilog design then you could also drive internal signals.