How to assign default values to variables declared with commonly used data-types?

SystemVerilog
1

Hi,

So while implementing a reset situation, I need to set some variables declared as integer as well as ‘logic {M - 1 : p]’ to their default values (Values that they take when first declared and nothing assigned to them.

The reason why I can’t assign them to zeros is because my implementation is such that even zero is a valid and acceptable input; again I need them to be like they have just been RE-DECLARED.

Any possible way to do this for varying data types, rather than looking up the LRM to check which data-type holds what default values?

2

In reply to Vedant Gala:

I faced the same situation, and see here for a possible solution. (The solution being UPF and power aware simulation.)

3

In reply to Vedant Gala:

The simplest method would be to declare a const variable without assigning it

const mytype mytype_default;