How to assign a variable name to a parameter?

SystemVerilog
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3

In reply to dave_59:
Hi,

I tried using the alias but a compile error says illegal operand for constant expression.
Here’s what I did:


// In this code, wire_var is triggerWrite0, while PARAM_1 is REGISTER_0_TRIGGER_WRITE
wire triggerWrite0;
assign triggerWrite0 = pm_trig[0];
alias triggerWrite0 = TRIG_WRITE0;
parameter REGISTER_0_TRIGGER_WRITE = TRIG_WRITE0; // Compile error points here

I’ll explain the situation in much further details later. I’m just looking for a better way to explain it simply.

Regards,
Reuben