In reply to Reuben:
You can’t do what you are trying to do in SystemVerilog. Are the parameters that are defined in a separate file included in the same module where both the wire_var and the port connection are located? If so you may want to look at using the alias construct. Otherwise, you will need to explain in a lot further detail the situation that brought you to this.
And there is no way to create an array of `defines within SystemVerilog.