I want to get a value from an internal RTL signal. The name of one of the module in the hierarchy keeps changing with every simulation run. So how do I get the hierarchy name correct every time.
For example I want to access a ‘valid’ signal which is at following hierarchy-
dut.top_l1.hardware_mod_xzzrtyu.valid
The “xzzrtyu” keeps changing with every simulation run.
I tried uvm_hdl_force, uvm_hdl_read, assign statement;I tried putting * but seems regex don’t work.
My DE is saying it’s a common practice. To be clear, the hierarchy path itself is not changing, it’s just that the module name suffix is randomized every run.
I have never used a tool which generates random names for module instances. This behavior seems counter intuitive to good design practices. Perhaps there is a tool option to disable this functionality so that you don’t have to deal with this issue.
You could possible do something with the VPI to search your design for what you are looking for, but it’s hard to say without knowing more about your environment.
The SystemVerilog Verification Procedural Interface (VPI) is part of the PLI. VPI provides a library of C language functions and a mechanism for associating foreign language functions with SystemVerilog user-defined system task and system function names.
One possibility is to update your flow to do the below :
Compile the RTL alone.
Have a script figure out what the new module name is for this compile.
Have the script update TB with this new name.
Compile TB.
Run simulations.
That said, if these modules are coming from a HLS tool that randomizes the names on each run, your DE could add a wrapper whose name doesn’t change, and bring out signals required for TB to this wrapper. That way the TB doesn’t have to change.
As suggested earlier, it’s best to disalbe this random postfix if possible and have a static name.