How make all the $random functions in my testbech to return same value

SystemVerilog
,
1

My test bench contains multiple $random system task calls in multiple files. There is a constraint that I cannot edit those files. With this given, is there a way to make all those $random system tasks return same value?. Assignment is to a single bit.

logic a,b;
a = $random;
b = $random;
This is just an example code. I want value of a and b to be same.

I looked in to lrm but couldn’t find any data regarding to my issue.
Is it possible to do so… with some thing like global seed etc…
Please let me know if there is a way to do this.

2

In reply to srikanthvvs1:

You can override the behavior of a system task by writing your own VPI implementation of it in C. That’s relatively easy if you want to override all calls to $random, but if only some, then it gets more complicated to know which ones, and you have to implement the normal behavior of $random for the others.

But this “I can’t edit the files” is nonsense. If you can read the file, you can edit a copy and replace it in the compilation process.

3

In reply to dave_59:

Thanks for the reply dave.

Here I’m working on soc verification and there are lots of different modules where this random forcing of a signal is happening. Even I don’t know all those files. That’s why I said I cannot edit those files

Can you please give me some details about this override.

Thanks.

4

In reply to srikanthvvs1:

See section 36.3.2 Overriding built-in system task and system function names in the 1800-2017 LRM.

But it’s not really clear what you are trying to accomplish.

5

In reply to dave_59:

Thanks Dave. I will look into the section you mentioned.

What I’m trying to do is,

We have dualsim GLS simulation which has both RTL and netlist run parallely.
There are few libraries which are common for both RTL and netlist. In that libraries initial values of clocks are being randomised. Due to this randomisation initial values for RTL and netlist differ so simulation goes out of sync for netlist and RTL.
Now I need to suppress this randomization to make initial values equal for netlist and RTL.

6

In reply to srikanthvvs1:

You could use force/release statements to do this. But you’ll probably want to write script to find all these clock initializations.

But really it would be sooo much easier to modify the code.