How make all the $random functions in my testbech to return same value

SystemVerilog
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3

In reply to dave_59:

Thanks for the reply dave.

Here I’m working on soc verification and there are lots of different modules where this random forcing of a signal is happening. Even I don’t know all those files. That’s why I said I cannot edit those files

Can you please give me some details about this override.

Thanks.