How does verilog deal with the fact that it doesn't allow user defined types

SystemVerilog
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In reply to Yasmine4:

do you have any idea how verilog programmers deal with this problem.?

They move to SystemVerilog. It’s been widely available for over a decade now in ASIC development. All of the major FPGA development tools have broad synthesis support of user defined type between 5-10 years. Why not move up from Verilog?

Dave