How does verilog deal with the fact that it doesn't allow user defined types

SystemVerilog
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In reply to Yasmine4:

How did Verilog designers deal with the lack of user-defined types? Well, we typed more, and used cut/paste more. And we ran into more dumb keyboarding mistakes, and cut/paste errors more often than we do today when using SystemVerilog.

To be truthful - for me at least - user-defined types are a nice to have, but I could still live without them. Multi-dimensional arrays as first class citizens in SystemVerilog? I could never go back to using Verilog without these multi-dimensional arrays.

Regards,

Mark