How do variable of base class type access property of derived class

SystemVerilog
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1

Here I have tried to mimic clone method of uvm_object.

typedef base_class;
typedef derived_class;
function base_class create();
  derived_class tmp;
  tmp = new();
  return tmp;
endfunction
class base_class;
  virtual function do_copy(base_class rhs);
  endfunction
  virtual function copy(base_class rhs);
	do_copy(rhs);
  endfunction
  virtual function base_class clone();
	base_class base;
    base = create();
	base.copy(this);
    return (base);
  endfunction
endclass
class derived_class extends base_class;
  int A = 5;
  function do_copy(base_class rhs);
	derived_class derived;
	$cast(derived,rhs);
	super.do_copy(rhs);
	A = derived.A;
  endfunction
  function display();
	$display("A is %0d",A);
  endfunction
endclass

module test();
  derived_class d1,d2;
  initial
  begin
	d1 = new();
	d1.A = 10;
    $cast(d2,d1.clone());
	d1.display();
	d2.display();
  end
endmodule

Output :
A is 10
A is 10

Here at base.copy(this);
“base” variable is of type base_class, how come it access variable “A” which is defined in derived_class?

Correct me if I am wrong somewhere.

2

In reply to Jinam Shah:

base.copy() calls do_copy(). Since do_copy() is a virtual method, it would call the derived_class::do_copy() -since “base” here is actually referencing a class object of type “derived_class”. So the access to “A” actually happened in the derived_class context. What is illegal is to do something like “base.A = 10;”