In reply to bhajanpreetsinght:
Eqs my paper: 1 Understanding the SVA Engine Using the Fork-Join Model
Using a model, the paper addresses important concepts about attempts and threads. Emphasizes the total independence of attempts.
At every clocking event you get a new attempt at eh assertion.
The “lock” does not stop the attempt. It just makes that attempt vacuous since the antecedent is zero.
I demonstrated in my example above that the action block resets the lock.
See my response above
The “pass” “fail” signals are just for debugging.
and the waveform https://photos.app.goo.gl/gSwHNhdMPKWbBWjT9
Are you just asking questions and not reading the replies.
If so, I am DONE with this thread!
I keep on repeating the same replies to your repeating questions
Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.
or Cohen_Links_to_papers_books - Google Docs
Getting started with verification with SystemVerilog