How can I convert string into dynamic parameterized array in system verilog?

SystemVerilog
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1

From Makefile, I am passing parameter string LINK2LANE=“8_4_2_1” to my top module. Now, from my top module,I want to convert this string into array. Ex. TB_LANES[`LINK-1:0]= {8,4,2,1} and pass it to child modules.
TB_LANES is parameterized array.

This both string and array are parameters,so I want to complete this task before taking instance of child module in my top module. It’s Urgent.

2

In reply to NIMESH CHAUDHARI:

If TB_LANES was just a variable, not a parameter, you could write code to convert the literal numbers in the string to decimal values and assign each value to an element of the array. But since it is a parameter, you cannot get that code to execute at compile time; which is needed to assign parameter values.

If you could define a macro like +define+L2L={8,4,2,1} from your Makefile, then you could write

TB_LANES[`LINK-1:0]= `L2L;
3

In reply to dave_59:

Thanks Dave,

now, I split my array in a perl script.
And I call that perl script from makefile. Now the problem is how can i store this array in my makefile?
And how can i define dynamic array in makefile?

4

In reply to NIMESH CHAUDHARI:
You are going to have to provide a lot more information, maybe too much for this forum.
You need to show what the code looks like that your are trying to parameterize, and an example of how you want to override it assuming you were doing this without a Makefile,
Then you need to show what perl script generates.