How can I convert string into dynamic parameterized array in system verilog?

SystemVerilog
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2

In reply to NIMESH CHAUDHARI:

If TB_LANES was just a variable, not a parameter, you could write code to convert the literal numbers in the string to decimal values and assign each value to an element of the array. But since it is a parameter, you cannot get that code to execute at compile time; which is needed to assign parameter values.

If you could define a macro like +define+L2L={8,4,2,1} from your Makefile, then you could write

TB_LANES[`LINK-1:0]= `L2L;