How can I assign one interface to another interface without manually connecting all signals?

SystemVerilog
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9

In reply to dave_59:

I still think an “interface alias” as I was brainstorming over here has potential.

https://verificationacademy.com/forums/systemverilog/multiple-interface-connections-multiple-dut

As this thread (again) shows, there’s certainly a need for this sort of construct in the SystemVerilog language.

Any chance something like this could be considered within the SystemVerilog working group?