How can I assign one interface to another interface without manually connecting all signals?

SystemVerilog
,
7

In reply to dave_59:

ok.
Can you retime an interface input port like this?..

always_ff @(posedge clk)
  my_interface_port_q <= my_intrface_port;

The need is to simply retime all the signals that come into a module.
A best practice for timing closure.