How can I assign one interface to another interface without manually connecting all signals?

SystemVerilog
,
6

In reply to mike_mentor:

Yes you can make procedural or continuous assignments from the signals inside one interface to another using hierarchical references. You would have to know the flow of data to know which direction to make the assignments.

If you were to use structures you would have to isolate the structures by direction. i.e. one structure for inputs and another for outputs.