How can I assign one interface to another interface without manually connecting all signals?

SystemVerilog
,
5

In reply to dave_59:

In reply to arquer:
Sorry, there is no way to tie two interfaces together.

For a module with an input interface port, can the interface wires be retimed
using a single assignment clocked process like this:

always_ff @(posedge clk)
  my_interface_port_q <= my_intrface_port;

Based on this thread, my guess is no.
Based on that if there is an interface port that needs to be retimed, all fields need to be broken out one at time like this:

always_ff @(posedge clk)
  begin
  first_sig_q <= my_inteface_port.first_sig;
  second_sig_q <= my_interface_port.second_sig;
  // ....
  end

Does that make sense that the signals have to be broken out to be retimed, or am I missing some easy way to retime all the signals in an interface?

A packed struct can be retimed, maybe this indicates a case where a packed struct port would be preferred over an interface.