Hierarchically accessing a SVA module from TB_top

SystemVerilog
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6

In reply to vk7715:

  1. A scope is an instance path name. The only time a module name works as a path name is an upwards reference (a top-level module is a kind of upward reference). You could use the bind construct to insert a module inside your sva_module.
  2. A list is comma separated: sva_module.assert_1, sva_module.assert_2

A better option might be to use your tools commands to turn on/off assertions which has much more flexibility in specifying paths (e.g. wildcards)