Hierarchically accessing a SVA module from TB_top

SystemVerilog
, , ,
5

In reply to dave_59:

Hi Dave, thank you for your answer. I took a look at the section you mentioned, and I have two questions:


$assertcontrol ( control_type [ , [ assertion_type ] [ , [ directive_type ] [ , [ levels ]
[ , list_of_scopes_or_assertions ] ] ] ] ) ;

  1. In the above code, if I want to enable/disable all assertions in an SVA module, can I give the name of the module in the “list_of_scopes_or_assertions” field instead of individually naming all the assertions?

  2. If I want to enable/disable just 2 assertions, do I specify them as

 assert_1 && assert_2

in the “list_of_scopes_or_assertions” field?