Hierarchically accessing a SVA module from TB_top

SystemVerilog
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3

In reply to dave_59:

Hi Dave, thank you for the answer. If not using defines, is there another way I can hierarchically control the assertions in the SVA module from TB_top?

To make it clear, this is the problem statement. I have some assertions in sva_module.sv, and I wish to control these assertions from TB_top and not make any changes to sva_module.sv (since this file is maintained by someone else).

Is there any way I can do this?

Please let me know.

Thanks,
VK