Hierarchically accessing a SVA module from TB_top

In reply to vk7715:

It is not possible to override the definition of abc the way you have written your sva_module.sv file from another file. You could if you had written it this way

module sva_module(<port list>);
`ifndef abc
  `define abc @(posedge clk)
`endif

AND you compile your module TB_top file with
`define abc
in it before the sva_module.sv file. You can also use a command line option
+define+abc=@(posedge clk) disable iff rst’
which overrides any compiler `define n the source code.

Because `define is a compiler directive, both these options apply to all instances of sva_module. You cannot have instance specific definitions of compiler directives.

If you require instance specific definitions, you need to provide a more complete example that describes how you plan instantiate sva_module.