Hierarchical referencing of an upper hierarchy from a lower hierarchy

SystemVerilog
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1 

// Let's say this is the hierarchy
my_tb_top.my_rtl_top.sub_mod0.sub_mod1.where_i_am

I know I can access signals in a hierarchy lower than where_i_am using hierarchical referencing.
And I also believe that I cannot access signals higher than where_i_am, except by using absolute referencing (i.e my_tb_top.****).

If I’m correct, then why is that I can still access signals in a higher hierarchy without using an absolute referencing?


// Inside where_i_am module, I can do this and the compilation is passing. How come?
logic probe_this;
assign probe_this = sub_mod0.signal_to_probe;
2

In reply to Reuben:

See section 23.8 Upwards name referencing in the 1800-2012 LRM

3

In reply to dave_59:

In reply to Reuben:
See section 23.8 Upwards name referencing in the 1800-2012 LRM

I see. So my knowledge about hierarchy referencing is already obsolete. It’s good that upward referencing is now possible.

4

In reply to Reuben:
It was always there in Verilog :)