Verification Academy
Hierarchical referencing of an upper hierarchy from a lower hierarchy
SystemVerilog
hierarchical-referencing
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absolute-reference
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SystemVerilog
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hierarchy-reference
dave_59
January 20, 2018, 2:14am
2
In reply to
Reuben
:
See section
23.8 Upwards name referencing
in the 1800-2012 LRM
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