In reply to feiphung:
pm the above example i only used the UVM messenging with severity levels’ there is a lot lot more to uvm. The Universal Verification Methodology (UVM) Class Reference addresses verification complexity and interoperability within companies and throughout the electronics industry for both novice and advanced teams while also providing consistency. UVM has claimed wide acceptance in the verification methodology of advanced designs. For the reporting of messages, UVM provides several macros that resemble the SystemVerilog severity levels, but provide more options and consistency with the UVM verification environment.
Ben