Help with assertion inside always@(*) combinational block alongside with for loop

SystemVerilog
,
4

In reply to feiphung:
I don’t see the issue here.


module m;
  `include "uvm_macros.svh"
     import uvm_pkg::*;
bit clk; 
bit[3:0] a=4, b=5, c; 
initial forever #10 clk=!clk;  
  
always_comb begin
    for (int i=0; i<=3; i++) begin
      assert(a[i] > b[i]) else $display("i a[i] b[i]", i, a[i], b[i]);        
      ap_ab: assert property(@ (posedge clk) a[i] |=> b[i]);  
    end    
end
        initial begin 
         repeat(20) begin 
             @(posedge clk);   
             if (!randomize(a, b)  with 
             { a dist {1'b1:=1, 1'b0:=1};
               b dist {1'b1:=1, 1'b0:=2};  
         }) `uvm_error("MYERR", "This is a randomize error");
         end 
         $finish; 
        end  
endmodule 
...
# KERNEL: i a[i] b[i]          100
# KERNEL: i a[i] b[i]          200
# KERNEL: i a[i] b[i]          300
# KERNEL: i a[i] b[i]          000
# KERNEL: i a[i] b[i]          100
# KERNEL: i a[i] b[i]          200
# KERNEL: i a[i] b[i]          300
# ASSERT: Error: ASRT_0005 testbench.sv(10): Assertion "ap_ab" FAILED at time: 50ns (3 clk), scope: m, start-time: 30ns (2 clk)
# ASSERT: Error: ASRT_0005 testbench.sv(10): Assertion "ap_ab" FAILED at time: 70ns (4 clk), scope: m, start-time: 50ns (3 clk)

Ben Cohen
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