Help in the assertion logic

SystemVerilog
,
1

Hi ,

The following statement is my scenario : dll_clk_ckfsm[17:0] been changed for every 2 clk of ckfsm.**

  • Every 2 clock cycles the register value changes “dll_clk_ckfsm”.
  • How to check for every 2 clocks the change is happening using assertion.

-Regards,
-Raja.

2 
ap1: assert property (@ (posedge clk) 
               ! $stable (sig) |-> ##2 ! $stable (sig));

    initial 
       begin
          wait (go);  // updated code
          ap0: assert property (@ (posedge clk) 
                ##2 ! $stable (sig));
        end

That’s a good start. You m a y need more small assertions, depending on your requirements.
Ben@systemverilog.us

3

In reply to ben@SystemVerilog.us:

HI BEN,

Yeah i may need more assertions…
Thanks for the soultion…
Forum helps me alot…

-Reagrds,
-Raja.