Help in the assertion logic

SystemVerilog
,
2 
ap1: assert property (@ (posedge clk) 
               ! $stable (sig) |-> ##2 ! $stable (sig));

    initial 
       begin
          wait (go);  // updated code
          ap0: assert property (@ (posedge clk) 
                ##2 ! $stable (sig));
        end

That’s a good start. You m a y need more small assertions, depending on your requirements.
Ben@systemverilog.us