Help about if statement in constraint block

SystemVerilog
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11

In reply to Reuben:

  
// Set the item
    this.pkt.randomize();
    this.pkt.cmd     = 1'b0;

With above code I understand you are overriding randmized packet and send the packet as read packing by changing cmd =0.

I believe, here your expectation is to the get pkt where cmd = 0 and data = {td,addr_inc, num_rd}; i.e randomized packet with read attribute if so, please try this one

  
// Set the item
    this.pkt.cmd     = 1'b0;
    this.pkt.cmd.rand_mode(0);
    this.pkt.randomize();

With this, it will always generate the read packet with as per your defined construct.

I am not sure, is this what you expecting here!