Help about if statement in constraint block

In reply to Naven8:

Hi Naven,

It looks it is working on you…
Maybe it is not working for me because I’m using this.pkt.randomize() in another function in another class.

I think it’s better if I’ll just paste all my codes here.

========================================================


`define ADR_SZ  15
`define DAT_SZ  8
`define CRC_SZ  4
`define TD_SZ   2 
`define I_SZ    2
`define NRD_SZ  4

`define AW        8
`define DBGDAT_SZ 28
`define TSTDAT_SZ 28
`define RDBK_SEL_SZ 2
`define LOG_SPACE 32767

class packet extends uvm_sequence_item;
  rand bit               cmd;
  rand bit [`ADR_SZ-1:0] addr;
  rand bit [`DAT_SZ-1:0] data;
       bit [`CRC_SZ-1:0] crc_key;

  rand bit [`TD_SZ-1:0]  td;
  rand bit [`I_SZ-1:0]   addr_inc;
  rand bit [`NRD_SZ-1:0] num_rd; 

  `uvm_object_utils_begin(packet)
     // I removed the part here since it's not related
  `uvm_object_utils_end

  constraint valid_addr {
    addr inside {[15'h0000:15'h6EFF], [15'h7F00:15'h7FFF]};
  }

  constraint solve_td_b4_data {
    solve td before cmd;
  }

  constraint solve_addr_inc_b4_data {
    solve addr_inc before cmd;
  }

  constraint solve_num_rd_b4_data {
    solve num_rd before cmd;
  }

  constraint solve_cmd_b4_data {
    solve cmd before data;
  }
 
  // To be deleted. For testing only
  constraint set_td {
    td == 2'b00;
  }

  // To be deleted. For testing only
  constraint set_addr {
    addr == 15'h4ba8;
  }

  // To be deleted. For tesing only
  constraint set_addr_inc {
    addr_inc == 2'b01;
  }

  constraint valid_num_rd {
    //num_rd != 0;
    num_rd == 4'h3;
  }

  constraint rd_cmd_data {
    if (cmd == 1'b0) {
      data == {td, addr_inc, num_rd};
    }  
  }

  function new(string name = "packet");
    super.new(name);

    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction
endclass

class rd_send_cmd_seq extends pkt_seq_base;
  `uvm_object_utils(rd_send_cmd_seq)

  function new(string name = "rd_send_cmd_seq");
    super.new(name);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction

  virtual task body();
    super.body();
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);

    // Ready the item
    start_item(pkt);

    // Set the item
    this.pkt.randomize();
    this.pkt.cmd     = 1'b0;
    this.pkt.crc_key = crc({this.pkt.cmd, this.pkt.addr, this.pkt.data},
                         `GEN_POL);

    // Go send the item
    finish_item(pkt);

    // Report the sent item
    `uvm_info($sformatf("rd_send_cmd_seq[%0d]", this.pkt.msg_id),
              {"\n", pkt.sprint()},
              UVM_MEDIUM);
  endtask
endclass

I know this is UVM but I think my problem is about System Verilog.